If you are involved with designing a board with an FPGA on it, starting with the schematics and ending in a functional PCB, then this article is four you ! Rationale Today more than ever, doing things quickly and right the first time is critical in any project. For HDL and Digital Design, we (...) -- IO Checker, HDL Works, IO Checker section, Introduction video, another video
Are you tempted about using Floating Point vectors (“Reals”) in your next FPGA project ? Can this be done ? How ? Is it a good idea ? Then this Application Note (an extract from our FPGA Design Training course) is for you… - Application Notes -- ieee754-2.jpg, floatingpoints_apnote-2.pdf, Application Notes
Are you tempted about using Floating Point vectors (“Reals”) in your next FPGA project ? Can this be done ? How ? Is it a good idea ? Then this Application Note (an extract from our FPGA Design Training course) is for you. - Intel -- ieee754.jpg, floatingpoints_apnote.pdf, Intel
In 2024, some may consider that UARTs (and RS232) are a thing of the past. They couldn't be more wrong ! An RS232 link is the simplest way to exchange any kind of information between to points ! From the simplest microprocessors to the most complex Systems On Chips and Embedded processors, all (...) -- rs232_scope1920.jpg, Application Notes
This section and its articles are dedicated to the technology of distributing real-time media contents over Ethernet and more specifically : Audio. We present briefly AVB and MILAN since we are launching in 2024 and AVB-Milan IP. AVB AVB “Audio Video Bridging” is a set of six IEEE standards (...) -- milan.jpg, AVB MILAN, AVB, Avnu Alliance, L-Acoustics, AVDECC Library
In 2024, ALSE launches an FPGA IP for Milan, thus allowing any company to develop products incorporating the MILAN technology and protocols in record time, with very low effort, and guaranteed performance and compliance. The ALSE Milan IP The ALSE Milan IP combines a complex FPGA Hardware (...) -- AVB MILAN
JESD204 is the Data Converter Serial Interface standard that was created through the JEDEC committee, with the participation of all the industrial providers of high-speed ADC and DACs (including Ti, Analog Devices etc). If you want to use High Speed ADCs or DACs in your project, you need an (...) -- jesd204b_datasheet.pdf, IPs
We have ported our Aurora 64B/66B on Polarfire, and tested it on the Polarfire kit. This is described in details in the Reference Design Documentation available below. In principle, this type of document is confidential and accessible only after signing a mutual NDA. Please understand that you (...) -- Microchip
Like we did for our Aurora 64B/66B, we have ported our Aurora 8B/10B on Polarfire, and tested it on the Polarfire kit. This is described in details in the Reference Design Documentation available below. In principle, this type of document is confidential and accessible only after signing a (...) -- Microchip
LiteX: Enhancing FPGA development with versatility and integration Author : Florent Kermarrec http://www.enjoy-digital.fr/ Overview of LiteX LiteX is an FPGA framework recognized for its broad compatibility with a range of FPGA platforms, including Lattice, Intel, Xilinx and and new actors (...) -- enjoydigital.jpg, Lattice, http://www.enjoy-digital.fr/, LiteX, ColorLite
This is an old Tutorial for a vintage kit ! Surprisingly, you'll see that the methodology shown here is still valid. This old tutorial show how to use the Igloo nano kit for implementing and testing a UART. It shows how things worked 15 years ago, and you might be surprised to see that things (...) -- alse_igloo_uart.pdf, Microchip
End 2023, we have ported several of our IPs on the Microchip Polarfire family, including our 10G Ethernet processor-less IP. In doing so, we have created a Reference Design for the MPF-300 EVAL Kit. The full documentation for this Reference Design is accessible below. - Microchip -- alse_10gedek_polarfire.pdf, Microchip
This IP is ideal to control a lot of peripherals from a centralized high-end (Master) FPGA (or ASIC) ! Connecting and controlling peripherals from the Master directly is typically difficult and inefficient : lack of support for 3.3V I/Os, level translators and ESD protections required, (...) -- chipbridge_datasheet.pdf, IPs
Practically all FPGAs, even the low cost ones, offer the capability to create high-speed communication links based on LVDS signalling. If you think it's complex to use this capability, this article will prove you wrong. LVDS (Low Voltage Differential Signalling) is a standard that uses two (...) -- lvds_logo.png, lvds-demo.pdf, Intel