A.L.S.E : Advanced Logic Synthesis for Electronics, vous propose des Services, des IPs, des Formations et des Cartes pour vos projets FPGA ou Logiciel Embarqué.
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Articles syndiqués tirés de ce site
- VHDL Examples
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Septembre 2016, par Bertrand Cuzeau
If you are looking for well-written code to analyze, or coding examples, please check also our Free IP section where you can find the source code of many IPs, which are reasonably simple to understand while implementing all the concepts needed for designing complex functions. We have dedicated (…)
- 10GEDEK
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Septembre 2016, par Bertrand Cuzeau
We have a 10G Ethernet version of our ground breaking GEDEK IP ! Yes, it’s 10 times fatser, and clearly, software solutions are unable to cope with such data rates (they couldn’t even address the Gigabit transfers without loss). 10G Ethernet ??? 10G Ethernet starts becoming available, if not (…)
- JPEG Video Decoder
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Septembre 2016, par Bertrand Cuzeau, Etienne Laurendeau, Frederic CALDAIROU
This compact and extremely efficient core is capable of decoding in real-time video on-the-fly using standard and ubiquitous JPEG compression, even on low-cost FPGAs. This IP does not require any processor nor any external memory. Purpose Our Baseline JPEG Decoder (Decompression) core is (…)
- And MANY more !
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Septembre 2016, par Bertrand Cuzeau
We probably already have the video processing block you need 😉 We have developed a lot of other video processing blocks : Frame Buffer Uses External Memory (typically DDRx) to buffer video frames and allow sender and receiver to operate at very slightly to very different rates. RGB ↔ 422 (…)
- EDID manager
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Septembre 2016, par Bertrand Cuzeau, Frederic CALDAIROU
This IP is actually two IPs in one and can manage the EDID Tables used in HDMI to let the sink (rx) disclose the video (and audio) formats that it supports. The two IP blocks are : EDID Table Provider This function includes an EDID Table provided by the user and an I2C Slave in order to manage (…)